In component testing, a common hardware problem is the skewing of a clock signal that indicates when a value is to be captured. A clock that has too much skew will cause a detected fault if the data on the line is changing. If the clock signal latches at a wrong time as a result of the clock skew, then the clock signal may latch where the data signal does not change and, as a result, the clock skew (error) is not detected.
Traditionally, a random data pattern is used to test the communication between two components. With a random data pattern, on average, 50% of the data values in the data lines will toggle (i.e., change in bit value from 1 to 0 or from 0 to 1) between two consecutive values. Therefore, there is a 50% chance of not detecting a clock skew problem.
Another prior solution is to use a sequential data pattern to test the communication between two components. With a sequential data pattern, on average, less than 2 bit lines will toggle. For 64 data lines, a sequential data pattern will cause less than 3.13% ((½^0+½^1+½^2+ . . . +½^63)/64) of the lines to change in value.
Therefore, the current technology is limited in its capabilities and suffers from at least the above constraints and deficiencies.